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general description the MAX17017 is a quad-output controller for ultra- mobile portable computers (umpcs) that rely on a low- power architecture. the MAX17017 provides a compact, low-cost controller capable of providing four indepen- dent regulatorsa main stage, a 3a p-p internal step- down, a 5a p-p internal step-down, and a 2a source/sink linear regulator. the main regulator can be configured as either a step- down converter (for 2 to 4 li+ cell applications) or as a step-up converter (for 1 li+ cell applications). the inter- nal switching regulators include 5v synchronous mosfets that can be powered directly from a single li+ cell or from the main 3.3v/5v power stages. finally, the linear regulator is capable of sourcing and sinking 2a to support ddr termination requirements or to generate a fixed output voltage. the step-down converters use a peak current-mode, fixed-frequency control schemean easy to implement architecture that does not sacrifice fast-transient response. this architecture also supports peak current- limit protection and pulse-skipping operation to maintain high efficiency under light-load conditions. separate enable inputs and independent open-drain power-good outputs allow flexible power sequencing. a soft-start function gradually ramps up the output volt- age to reduce the inrush current. disabled regulators enter high-impedance states to avoid negative output voltage created by rapidly discharging the output through the low-side mosfet. the MAX17017 also includes output undervoltage, output overvoltage, and thermal-fault protection. the MAX17017 is available in a 48-pin, 6mm x 6mm thin qfn package. applications 1-to-4 li+ cell battery-powered devices low-power architecture ultra-mobile pc (umpc) portable gaming notebook and subnotebook computers pdas and mobile communicators features fixed-frequency, current-mode controllers 5.5v to 28v input range (step-down) or 3v to 5v input range (step-up) 1x step-up or step-down controller 1x internal 5a p-p step-down regulator 1x internal 3a p-p step-down regulator 1x 2a source/sink linear regulator with dynamic refin internal bst diodes internal 5v, 50ma linear regulator fault protection?ndervoltage, overvoltage, thermal, peak current limit independent enable inputs and power-good outputs voltage-controlled soft-start high-impedance shutdown 10? (typ) shutdown current MAX17017 quad-output controller for low-power architecture ________________________________________________________________ maxim integrated products 1 MAX17017 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 cspa csna agnd ref freq up/dn ina v cc byp ldo5 inldo shdn onb sync ona inbc inbc inbc inbc v dd pokd ond onc fbc 37 38 39 40 41 42 43 44 45 46 47 48 1 pokc bstc lxc lxc lxc lxc outd outd ind fbd vttr refind fbb pokb bstb lxb lxb lxb dla bsta lxa dha poka fba + 2 3 4 5 6 7 8 9 10 11 12 exposed pad = gnd thin qfn top view pin configuration ordering information 19-4121; rev 2; 6/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17017gtm+ -40c to +105c 48 tqfn-ep*
MAX17017 quad-output controller for low-power architecture 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. inldo, shdn to gnd............................................-0.3v to +28v ldo5, ina, v dd , v cc to gnd ..................................-0.3v to +6v dha to lxa .............................................-0.3v to (v bsta + 0.3v) ona, onb, onc, ond to gnd ...............................-0.3v to +6v poka, pokb, pokc, pokd to gnd .........-0.3v to (v cc + 0.3v) ref, refind, freq, up /dn, sync to gnd ........................................-0.3v to (v cc + 0.3v) fba, fbb, fbc, fbd to gnd .....................-0.3v to (v cc + 0.3v) byp to gnd ............................................-0.3v to (v ldo5 + 0.3v) cspa, csna to gnd .................................-0.3v to (v cc + 0.3v) dla to gnd................................................-0.3v to (v dd + 0.3v) inbc, ind to gnd....................................................-0.3v to +6v outd to gnd............................................-0.3v to (v ind + 0.3v) vttr to gnd.............................................-0.3v to (v byp + 0.3v) lxb, lxc to gnd ....................................-1.0v to (v inbc + 0.3v) bstb to gnd ....................................(v dd - 0.3v) to (v lxb + 6v) bstc to gnd ....................................(v dd - 0.3v) to (v lxc + 6v) bsta to gnd ....................................(v dd - 0.3v) to (v lxa + 6v) ref short-circuit current......................................................1ma continuous power dissipation (t a = +70c) multilayer pcb: 48-pin 6mm x 6mm 2 tqfn (t4866-2 derated 37mw/c above +70c) ....................2.9w operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) ................................+300c t a = 0? to +85? parameter symbol conditions min typ max units up /dn = gnd (step-up), ina 3.0 5.0 input voltage range up /dn = ldo5 (step-down), inldo, ina = ldo5 5.5 24 v up /dn = gnd (step-up), ina = inldo, rising edge hysteresis = 100mv 2.5 2.7 2.9 ina undervoltage threshold v ina ( uvlo ) up /dn = ldo5 (step-down), ina = v cc , rising edge, hysteresis = 160mv 4.0 4.2 4.4 v inbc input voltage range 2.3 5.5 v minimum step-up startup voltage up /dn = gnd (step-up) 2.9 3.0 v supply currents v inldo shutdown supply current i in ( shdn ) v in = 5.5v to 26v, shdn = gnd 10 15 a v inldo suspend supply current i in(sus) v inldo = 5.5v to 26v, on_ = gnd, shdn = inldo 50 80 a v cc shutdown supply current shdn = ona = onb = onc = ond = gnd, t a = +25c 0.1 1 a v dd shutdown supply current shdn = ona = onb = onc = ond = gnd, t a = +25c 0.1 1 a ina shutdown current i ina shdn = ona = onb = onc = ond = gnd, up /dn = v cc 710a v cc supply current main step-down only ona = v cc , onb = onc = ond = gnd; does not include switching losses, measured from v cc 210 300 a
MAX17017 quad-output controller for low-power architecture _______________________________________________________________________________________ 3 t a = 0? to +85? parameter symbol conditions min typ max units v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator b ona = onb = v cc , onc = ond = gnd; does not include switching losses, measured from v cc 280 350 a v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator c ona = onc = v cc , onb = ond = gnd; does not include switching losses, measured from v cc 280 350 a v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator d ona = ond = v cc , onb = onc = gnd; does not include switching losses; measured from v cc 2.2 3 ma ina supply current (step-down) i ina ona = v cc , up /dn = v cc (step-down) 40 60 a in a + v c c s tep - u p s up p l y c ur r ent i ina ona = v cc , up /dn = gnd (step-up) 320 410 a 5v linear regulator (ldo5) ldo5 output voltage v ldo5 v inldo = 5.5v to 26v, i ldo5 = 0 to 50ma, byp = gnd 4.8 5.0 5.2 v ldo5 short-circuit current limit ldo5 = byp = gnd 70 160 250 ma byp switchover threshold v byp rising edge 4.65 v ldo5-to-byp switch resistance r byp ldo5 to byp, v byp = 5v, i ldo5 = 50ma 1.5 4 _ 1.25v reference reference output voltage v ref no load 1.237 1.25 1.263 v reference load regulation _ v ref i ref = -1a to +50a 3 10 mv reference undervoltage lockout v ref ( uvlo ) 1.0 v oscillator freq = v cc 500 freq = ref 750 khz oscillator frequency f osc freq = gnd 0.9 1.0 1.1 mhz f swa main step-up/step-down (regulator a) 1/2 f osc f swb regulator b f osc switching frequency f swc regulator c 1/2 f osc mhz maximum duty cycle (all switching regulators) d max 90 93.5 % freq = v cc or gnd 90 minimum on-time (all switching regulators) t on(min) freq = ref 75 ns regulator a (main step-up/step-down) step-up configuration ( up /dn = gnd) 3.0 v cc + 0.3 output-voltage adjust range step-down configuration ( up /dn = v cc ) 1.0 v cc + 0.3 v electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1)
MAX17017 quad-output controller for low-power architecture 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1) t a = 0? to +85? parameter symbol conditions min typ max units step-up configuration ( up /dn = gnd), v cspa - v csna = 0 to 20mv, 90% duty cycle 0.975 0.99 1.013 fba regulation voltage v fba step-down configuration ( up /dn = v cc ), v cspa - v csna = 0mv, 90% duty cycle 0.968 0.97 1.003 v step-up configuration ( up /dn = gnd), v cspa - v csna = 0mv, 90% duty cycle 0.959 1.013 fba regulation voltage (overload) v fba step-down configuration ( up /dn = v cc ), v cspa - v csna = 0 to 20mv, 90% duty cycle 0.930 1.003 v step-up configuration ( up /dn = gnd), v cspa - v csna = 0 to 20mv -20 fba load regulation v fba step-down configuration ( up /dn = v cc ), v cspa - v csna = 0 to 20mv -40 mv step-up ( up /dn = gnd) 51016 fba line regulation up /dn = gnd or v cc , 0 to 100% duty cycle step-down ( up /dn = v cc ) 10 16 22 mv fba input current i fba up /dn = gnd or v cc , t a = +25c -100 -5 +100 na current-sense input common- mode range v csa 0 v cc + 0.3v v current-sense input bias current i csa t a = +25c 40 60 a current-limit threshold (positive) v ilima 18 20 22 mv idle mode? threshold v idlea 4mv zero-crossing threshold v izx 1mv dha gate driver on-resistance r dh dha forced high and low 2.5 5 dla forced high 2.5 5 dla gate driver on-resistance r dl dla forced low 1.5 3 dha gate driver source/sink current i dh dha forced to 2.5v 0.7 a i dl(src) dla forced to 2.5v 0.7 dla gate driver source/sink current i dl(snk) dla forced to 2.5v 1.5 a bsta switch on-resistance r bsta 5 idle mode is a trademark of maxim integrated products, inc.
MAX17017 quad-output controller for low-power architecture _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1) t a = 0? to +85? parameter symbol conditions min typ max units regulator b (internal 3a step-down converter) fbb regulation voltage i lxb = 0% duty cycle (note 2) 0.747 0.755 0.762 v fbb reg ul ati on v ol tag e ( over l oad ) v fbb i lxb = 0 to 2.5a, 0% duty cycle (note 2) 0.720 0.762 v fbb load regulation v fbb / i lxb i lxb = 0 to 2.5a -5 mv/a fbb line regulation 0 to 100% duty cycle 7 8 10 mv fbb input current i fbb t a = +25c -100 -5 +100 na high-side n-channel 75 150 internal mosfet on-resistance low-side n-channel 40 80 m lxb peak current limit i pkb 3.0 3.45 4.0 a lxb idle-mode trip level i idleb 0.8 a lxb zero-crossing trip level i zxb 100 ma lxb leakage current i lxb onb = gnd, v lxb = gnd or 5v; v inbc = 5v at t a = +25c -20 +20 a regulator c (internal 5a step-down converter) fbc regulation voltage i lxc = 0a, 0% duty cycle (note 2) 0.747 0.755 0.762 v fbc reg ul ati on v ol tag e ( over l oad ) v fbc i lxc = 0 to 4a, 0% duty cycle (note 2) 0.710 0.762 v fbc load regulation v fbc / i lxc i lxc = 0 to 4a -7 mv/a fbc line regulation 0 to 100% duty cycle 12 14 16 mv fbc input current i fbc t a = +25c -100 -5 +100 na high-side n-channel 50 100 internal mosfet on-resistance low-side n-channel 25 40 m lxc peak current limit i pkc 5.0 5.75 6.5 a lxc idle-mode trip level i idlec 1.2 a lxc zero-crossing trip level i zxc 100 ma lxc leakage current i lxc onc = gnd, v lxc = gnd or 5v; v inbc = 5v at t a = +25c -20 +20 a regulator d (source/sink linear regulator and vttr buffer) ind input voltage range v ind 1 2.8 v ind supply current ond = v cc 10 50 a ind shutdown current ond = gnd, t a = +25c 10 a refind input range 0.5 1.5 v refind input bias current v refind = 0 to 1.5v, t a = +25c -100 +100 na outd output voltage range v outd 0.5 1.5 v v fbd with respect to v refind , outd = fbd, i outd = +50a (source load) -10 0 fbd output accuracy v fbd v fbd with respect to v refind , outd = fbd, i outd = -50a (sink load) 0 +10 mv fbd load regulation i outd = 1a -17 -13 mv/a
MAX17017 quad-output controller for low-power architecture 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1) t a = 0? to +85? parameter symbol conditions min typ max units fbd line regulation v ind = 1.0v to 2.8v, i outd = 200ma 1 mv fbd input current v fbd = 0 to 1.5v, t a = +25c 0.1 0.5 a source load +2 +4 outd linear regulator current limit sink load -2 -4 a current-limit soft-start time with respect to internal ond signal 160 s high-side on-resistance 120 250 internal mosfet on-resistance low-side on-resistance 180 450 m i vttr = 0.5ma -10 +10 vttr output accuracy refind to vttr i vttr = 3ma -20 +20 mv vttr maximum current rating 5 ma fault protection upper threshold rising edge, hysteresis = 50mv 91214 smps pok and fault thresholds lower threshold falling edge, hysteresis = 50mv -14 -12 -9 % upper threshold rising edge, hysteresis = 50mv 61216 vtt ldo pokd and fault threshold lower threshold falling edge, hysteresis = 50mv -16 -12 -6 % pok propagation delay t pok fb_ forced 50mv beyond pok_ trip threshold 5s overvoltage fault latch delay t ovp fb_ forced 50mv above pok_ upper trip threshold 5s smps undervoltage fault latch delay t uvp fba, fbb, or fbc forced 50mv below pok_ lower trip threshold 5s vtt ldo undervoltage fault latch delay t uvp fbd forced 50mv below pokd lower trip threshold 5000 s pok output low voltage v pok i sink = 3ma 0.4 v pok leakage currents i pok v f b a = 1.05v , v f b b = v f b c = 0.8v , v f b d = v r e fi n d + 50m v ( p o k hi g h i m p ed ance) ; pok_ forced to 5v, t a = +25c 1a thermal-shutdown threshold t shdn hysteresis = 15c 160 c general logic levels shdn input logic threshold hysteresis = 20mv 0.5 1.6 v shdn input bias current t a = +25c -1 +1 a on_ input logic threshold hysteresis = 170mv 0.5 1.6 v on_ input bias current t a = +25c -1 +1 a up /dn input logic threshold 0.5 1.6 v up /dn input bias current t a = +25c -1 +1 a
MAX17017 quad-output controller for low-power architecture _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = 0? to +85? , unless other- wise noted. typical values are at t a = +25c.) (note 1) t a = 0? to +85? parameter symbol conditions min typ max units high (v cc )v cc - 0.4v unconnected/ref 1.65 3.8 freq input voltage levels low (gnd) 0.5 v freq input bias current t a = +25c -2 +2 a sync input logic threshold 1.5 3.5 v sync input bias current t a = +25c -1 +1 a electrical characteristics (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = -40? to +105? .) (note 1) t a = -40? to +105? parameter symbol conditions min typ max units up /dn = gnd (step-up), ina 3.0 5.0 input voltage range up /dn = ldo5 (step-down), inldo, ina = ldo5 5.5 24 v up /dn = gnd (step-up), ina = inldo, rising edge, hysteresis = 100mv 2.4 3.0 ina undervoltage threshold v ina(uvlo ) up /dn = ldo5 (step-down), ina = v cc , rising edge, hysteresis = 160mv 3.9 4.5 v inbc input voltage range 2.3 5.5 v minimum step-up startup voltage up /dn = gnd (step-up) 3.0 v supply currents v inldo shutdown supply current i in ( shdn ) v in = 5.5v to 26v, shdn = gnd 15 a v inldo suspend supply current i in ( sus ) v inldo = 5.5v to 26v, on_ = gnd, shdn = inldo 80 a ina shutdown current i ina shdn = ona = onb = onc = ond = gnd, up /dn = v cc 10 a v cc supply current main step-down only ona = v cc , onb = onc = ond = gnd; does not include switching losses, measured from v cc 350 a v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator b ona = onb = v cc , onc = ond = gnd; does not include switching losses, measured from v cc 400 a v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator c ona = onc = v cc , onb = ond = gnd, does not include switching losses, measured from v cc 400 a
MAX17017 quad-output controller for low-power architecture 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = -40? to +105? .) (note 1) t a = -40? to +105? parameter symbol conditions min typ max units v c c s up p l y c ur r ent m ai n s tep - d ow n and reg ul ator d ona = ond = v cc , onb = onc = gnd, does not include switching losses, measured from v cc 3.5 ma ina supply current (step-down) i ina ona = v cc , up /dn = v cc (step-down) 75 in a + v c c s tep - u p s up p l y c ur r ent i ina ona = v cc , up /dn = gnd (step-up) 475 a 5v linear regulator (ldo5) ldo5 output voltage v ldo5 v inldo = 5.5v to 26v, i ldo5 = 0 to 50ma, byp = gnd 4.75 5.25 v ldo5 short-circuit current limit ldo5 = byp = gnd 55 ma 1.25v reference reference output voltage v ref no load 1.237 1.263 v reference load regulation v ref i ref = -1a to +50a 12 mv oscillator oscillator frequency f osc freq = gnd 0.9 1.1 mhz maximum duty cycle (all switching regulators) d max 89 % regulator a (main step-up/step-down) step-up configuration ( up /dn = gnd) 3.0 v cc + 0.3v output-voltage adjust range step-down configuration ( up /dn = v cc ) 1.0 v cc + 0.3v v step-up configuration, v cspa - v csna = 0mv, 90% duty cycle 0.970 1.018 fba regulation voltage step-down configuration, v cspa - v csna = 0mv, 90% duty cycle 0.963 1.008 v step-up configuration ( up /dn = gnd), v c s p a - v c s n a = 0 to 20m v , 90% d uty cycl e 0.954 1.018 fba regulation voltage (overload) v fba step-down configuration ( up /dn = v cc ), v c s p a - v c s n a = 0 to 20m v , 90% d uty cycl e 0.925 1.008 v step-up ( up /dn = gnd) 5 19 fba line regulation step-down ( up /dn = v cc )1023 mv current-sense input common- mode range v csa 0 v cc + 0.3v v current-limit threshold (positive) v ilima 17 23 mv
MAX17017 quad-output controller for low-power architecture _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = -40? to +105? .) (note 1) t a = -40? to +105? parameter symbol conditions min typ max units regulator b (internal 3a step-down converter) fbb reg ul ati on v ol tag ei lxb = 0a, 0% duty cycle (note 2) 0.742 0.766 v fbb reg ul ati on v ol tag e ( over l oad ) v fbb i lxb = 0 to 2.5a , 0% duty cycle (note 2) 0.715 0.766 v fbb line regulation 612mv lxb peak current limit i pkb 2.7 4.2 a regulator c (internal 5a step-down converter) fbc reg ul ati on v ol tag ei lxc = 0a, 0% duty cycle (note 2) 0.742 0.766 v fbc reg ul ati on v ol tag e ( over l oad ) v fbc i lxc = 0 to 4a, 0% duty cycle (note 2) 0.705 0.766 v fbc line regulation 11 20 mv lxc peak current limit i pkc 5.0 6.5 a regulator d (source/sink linear regulator and vttr buffer) ind input voltage range v ind 1 2.8 v ind supply current ond = v cc 70 a refind input range 0.5 1.5 v outd output voltage range v outd 0.5 1.5 v v f bd w i th r esp ect to v r e f in d , o u td = fbd , i ou t d = + 50a ( sour ce l oad ) -12 0 fbd output accuracy v fbd v fbd with respect to v refind , outd = fbd, i outd = -50a (sink load) 0 +12 mv fbd load regulation i outd = 1a -20 mv/a source load +2 +4 outd linear regulator current limit sink load -2 -4 a high-side on-resistance 300 internal mosfet on-resistance low-side on-resistance 475 m vttr output accuracy refind to vttr i vttr = 3ma -20 +20 mv
MAX17017 quad-output controller for low-power architecture 10 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 (step-down), v inldo = 12v, v ina = v inbc = v dd = v cc = v byp = v cspa = v csna = 5v, v ind = 1.8v, v shdn = v ona = v onb = v onc = v ond = 5v, i ref = i ldo5 = i outd = no load, freq = gnd, up /dn = v cc , t a = -40? to +105? .) (note 1) t a = -40c to +105c parameter symbol conditions min typ max units fault protection upper threshold rising edge, hysteresis = 50mv 8 16 smps pok and fault thresholds lower threshold falling edge, hysteresis = 50mv -16 -8 % upper threshold rising edge, hysteresis = 50mv 6 16 vtt ldo pokd and fault threshold lower threshold falling edge, hysteresis = 50mv -16 -6 % pok output low voltage v pok i sink = 3ma 0.4 v general logic levels shdn input logic threshold hysteresis = 20mv 0.5 1.6 v on_ input logic threshold hysteresis = 170mv 0.5 1.6 v up /dn input logic threshold 0.5 1.6 v high (v cc ) v cc - 0.4v unconnected/ref 1.65 3.8 freq input voltage levels low (gnd) 0.5 v sync input logic threshold 1.5 3.5 v note 1: limits are 100% production tested at t a = +25c. maximum and minimum limits are guaranteed by design and characterization. note 2: regulation voltage tested with slope compensation. the typical value is equivalent to 0% duty cycle. in real application, the regulation voltage is higher due to the line regulation times the duty cycle.
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 11 smps regulator a efficiency vs. load current MAX17017 toc01 load current (a) efficiency (%) 1 0.1 0.01 55 60 65 70 75 80 85 90 95 100 50 0.001 10 v in = 20v v in = 12v v in = 8v smps regulator a output voltage vs. load current MAX17017 toc02 load current (a) output voltage (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.80 4.85 4.90 4.95 5.00 5.05 4.75 0 5.0 v in = 20v v in = 12v v in = 8v smps regulator b efficiency vs. load current MAX17017 toc03 load current (a) efficiency (%) 1 0.1 0.01 55 60 65 70 75 80 85 90 95 100 50 0.001 10 v in = 3.3v v in = 5v v in = 2.5v smps regulator b output voltage vs. load current MAX17017 toc04 load current (a) output voltage (v) 1.5 2.0 2.5 1.0 0.5 1.77 1.82 1.72 0 3.0 v in = 3.3v v in = 5v v in = 2.5v smps regulator c efficiency vs. load current MAX17017 toc05 load current (a) efficiency (%) 1 0.1 0.01 55 60 65 70 75 80 85 90 50 0.001 10 v in = 3.3v v in = 5v v in = 2.5v smps regulator c output voltage vs. load current MAX17017 toc06 load current (a) output voltage (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0.98 05.0 v in = 3.3v v in = 5v v in = 2.5v regulator d voltage vs. source/sink load current MAX17017 toc07 load current (a) vtt voltage (v) 1.5 1.0 0 0.5 -1.0 -0.5 -1.5 0.885 0.890 0.895 0.900 0.905 0.910 0.915 0.920 0.925 0.930 0.880 -2.0 2.0 typical operating characteristics (circuit of figure 1, t a = +25c, unless otherwise noted.)
MAX17017 quad-output controller for low-power architecture 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, t a = +25c, unless otherwise noted.) reg b startup waveform (heavy load) MAX17017 toc10 400 s/div onb outb pokb i lb lxb onb: 5v/div outb: 2v/div pokb: 5v/div i lb : 2a/div lxb: 5v/div r load = 1.01 reg b shutdown waveform MAX17017 toc11 400 s/div onb outb pokb i lb lxb onb: 5v/div outb: 2v/div pokb: 5v/div i lb : 2a/div lxb: 5v/div r load = 0.8 reg c startup waveform (heavy load) MAX17017 toc12 400 s/div onc outc pokc i lc lxc onc: 5v/div outc: 1v/div pokc: 5v/div i lc : 5a/div lxc: 5v/div r load = 0.25 reg c shutdown MAX17017 toc13 100 s/div onc outc pokc i lc lxc onc: 5v/div outc: 1v/div pokc: 5v/div i lc : 5a/div lxc: 5v/div r load = 0.25 reg a startup waveform (heavy load) MAX17017 toc08 400 s/div ona outa poka i la lxa ona: 5v/div outa: 5v/div poka: 5v/div i la : 5a/div lxa: 10v/div r load = 1.6 reg a shutdown waveform MAX17017 toc09 400 s/div ona outa poka i la lxa ona: 5v/div outa: 5v/div poka: 5v/div i la : 5a/div lxa: 10v/div r load = 2.5
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 13 reg a load transient (1a to 3.2a) MAX17017 toc14 20 s/div outa i outa i la lxa outa: 100mv/div lxa: 10v/div i la : 2a/div i outa : 2a/div v ina = 12v, load transient is from 1a to 3.2a reg b load transient (0.4a to 2a) MAX17017 toc15 20 s/div outb i outb i lb lxb outb: 50mv/div lxb: 5v/div i lb : 1a/div i outb : 2a/div v inbc = 5v, 0.4a to 2.0a load transient reg c load transient (0.8a to 3a) MAX17017 toc16 20 s/div outc i outc i lc lxc outc: 50mv/div lxc: 5v/div i lc : 2a/div i outc : 2a/div v inbc = 5v, 0.8a to 3.0a load transient reg d load transient (source/sink) MAX17017 toc17 20 s/div i outd outd outd: 20mv/div i outd : 1a/div ind = 1.8v, refind = 0.9v, c out = 2 x 10 f, load transient is from 1a sourcing to 1a sinking reg d load transient (sink) MAX17017 toc18 20 s/div i outd outd outd: 10mv/div i outd : 1a/div ind = 1.8v, refind = 0.9v, c out = 2 x 10 f, load transient is from 0 to 1a sinking typical operating characteristics (continued) (circuit of figure 1, t a = +25c, unless otherwise noted.) reg d load transient (source) MAX17017 toc19 20 s/div i outd outd outd: 10mv/div i outd : 1a/div ind = 1.8v, refind = 0.9v, c out = 2 x 10 f, load transient is from 0 to 1a sourcing
MAX17017 quad-output controller for low-power architecture 14 ______________________________________________________________________________________ pin description pin name function 1pokc open-drain power-good output for the internal 5a step-down converter. pokc is low if fbc is more than 12% (typ) above or below the nominal 0.75v feedback regulation threshold. pokc is held low during startup and in shutdown. pokc becomes high impedance when fbc is in regulation. 2 bstc boost flying capacitor connection for the internal 5a step-down converter. the MAX17017 includes an internal boost switch/diode connected between v dd and bstc. connect to an external capacitor as shown in figure 1. 3C6 lxc inductor connection for the internal 5a step-down converter. connect lxc to the switched side of the inductor. 7, 8 outd source/sink linear regulator output. bypass outd with 2x 10f or greater ceramic capacitors to ground. dropout needs additional output capacitance (see the vtt ldo output capacitor selection (c outd ) section). 9inds our ce/s i nk li near reg ul ator inp ut. byp ass in d w i th a 10f or g r eater cer am i c cap aci tor to g r ound . 10 fbd feedback input for the internal source/sink linear regulator. fbd tracks and regulates to the refind voltage. 11 vttr ouput of reference buffer. bypass with 0.22f for 3ma of output current. 12 refind dynamic reference input voltage for the source/sink linear regulator and the reference buffer. the linear regulator feedback threshold (fbd) tracks the refind voltage. 13 shdn shutdown control input. the device enters its 5a supply current shutdown mode if v shdn is less than the shdn input falling edge trip level and does not restart until v shdn is greater than the shdn input rising edge trip level. connect shdn to v inldo for automatic startup of ldo5. 14 inldo input of the startup circuitry and the ldo5 internal 5v linear regulator. bypass to gnd with a 0.1f or greater ceramic capacitor close to the controller. in the single-cell step-up applications, the 5v linear regulator is no longer necessary for the 5v bias supply. connect byp and inldo to the systems 5v supply to effectively disable the linear regulator. 15 ldo5 5v internal linear regulator output. bypass with a 4.7f or greater ceramic capacitor. the 5v linear regulator provides the bias power for the gate drivers (v dd ) and analog control circuitry (v cc ). the linear regulator sources up to 50ma (max guaranteed). when byp exceeds 4.65v (typ), the MAX17017 bypasses the linear regulator through a 1.5 _ bypass switch. when the linear regulator is bypassed, ldo5 supports loads up to 100ma. in the single-cell step-up applications, the 5v linear regulator is no longer necessary for the 5v bias supply. bypass shdn to ground and leave ldo5 unconnected. connect byp and inldo to effectively disable the linear regulator. 16 byp linear regulator bypass input. when byp exceeds 4.65v, the controller shorts ldo5 to byp through a 1.5 _ bypass switch and disables the linear regulator. when byp is low, the linear regulator remains active. the byp input also serves as the vttr buffer supply, allowing vttr to remain active even when the source/sink linear regulator (outd) has been disabled under system standby/suspend conditions. in the single-cell step-up applications, the 5v linear regulator is no longer necessary for the 5v bias supply. bypass ldo5 to ground with a 1f capacitor and leave this output unconnected. connect byp and inldo to the systems 5v supply to effectively disable the linear regulator.
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 15 pin description (continued) pin name function 17 v cc 5v analog bias supply. v cc powers all the analog control blocks (error amplifiers, current-sense amplifiers, fault comparators, etc.) and control logic. connect v cc to the 5v system supply with a series 10 _ resistor, and bypass to analog ground using a 1f or greater ceramic capacitor. 18 ina input to the circuit in reg a in boost mode. connect ina to the input in step-up mode ( up /dn = gnd) and connect ina to ldo5 in step-down mode ( up /dn = v cc ). 19 up /dn converter configuration selection input for regulator a. when up /dn is pulled high ( up /dn = v cc ), regulator a operates as a step-down converter (figure 1). when up /dn is pulled low ( up /dn = gnd), regulator a operates as a step-up converter. 20 freq trilevel oscillator frequency selection input. freq = v cc : rega = 250khz, regb = 500khz, regc = 250khz freq = ref: rega = 375khz, regb = 750khz, regc = 375khz freq = gnd: rega = 500khz, regb = 1mhz, regc = 500khz 21 ref 1.25v reference-voltage output. bypass ref to analog ground with a 0.1f ceramic capacitor. the reference sources up to 50a for external loads. loading ref degrades output voltage accuracy according to the ref load-regulation error. the reference shuts down when the system pulls shdn low in buck mode ( up /dn = gnd) or when the system pulls ona low in boost mode ( up /dn = v cc ). 22 agnd analog ground 23 csna n eg ati ve c ur r ent- s ense inp ut for the m ai n s w i tchi ng reg ul ator . c onnect to the neg ati ve ter m i nal of the cur r ent- sense r esi stor . d ue to the c s n a b i as cur r ent r eq ui r em ents, l i m i t the ser i es i m p ed ance to l ess than 10 ? . 24 cspa p osi ti ve c ur r ent- s ense inp ut for the m ai n s w i tchi ng reg ul ator . c onnect to the p osi ti ve ter m i nal of the cur r ent- sense r esi stor . d ue to the c s p a b i as cur r ent r eq ui r em ents, l i m i t the ser i es i m p ed ance to l ess than 10 . 25 fba feedback input for the main switching regulator. fba regulates to 1.0v. 26 poka open-drain power-good output for the main switching regulator. poka is low if fba is more than 12% (typ) above or below the nominal 1.0v feedback regulation point. poka is held low during soft-start and in shutdown. poka becomes high impedance when fba is in regulation. 27 dha high-side gate-driver output for the main switching regulator. dha swings from lxa to bsta. 28 lxa inductor connection of converter a. connect lxa to the switched side of the inductor. 29 bsta boost fl yi ng c ap aci tor c onnecti on of c onver ter a. the m ax 17017 i ncl ud es an i nter nal b oost sw i tch/d i od e connected b etw een v dd and bs ta. c onnect to an exter nal cap aci tor as show n i n fi g ur e 1. 30 dla low-side gate-driver output for the main switching regulator. dla swings from gnd to v dd . 31, 32, 33 lxb inductor connection for the internal 3a step-down converter. connect lxb to the switched side of the inductor. 34 bstb boost flying capacitor connection for the internal 3a step-down converter. the MAX17017 includes an internal boost switch/diode connected between v dd and bstb. connect to an external capacitor as shown in figure 1. 35 pokb open-drain power-good output for the internal 3a step-down converter. pokb is low if fbb is more than 12% (typ) above or below the nominal 0.75v feedback-regulation threshold. pokb is held low during soft- start and in shutdown. pokb becomes high impedance when fbb is in regulation.
MAX17017 quad-output controller for low-power architecture 16 ______________________________________________________________________________________ pin description (continued) pin name function 36 fbb feedback input for the internal 3a step-down converter. fbb regulates to 0.75v. 37 onb switching regulator b enable input. when onb is pulled low, lxb is high impedance. when onb is driven high, the controller enables the 3a internal switching regulator. 38 sync external synchronization input. used to override the internal switching frequency. 39 ona switching regulator a enable input. when ona is pulled low, dla and dha are pulled low. when ona is driven high, the controller enables the step-up/step-down converter. 40C43 inbc input for regulators b and c. power inbc from a 2.5v to 5.5v supply. internally connected to the drain of the high-side mosfets for both regulator b and regulator c. bypass to pgnd with 2x 10f or greater ceramic capacitors to support the rms current. 44 v dd 5v bias supply input for the internal switching regulator drivers. bypass with a 1f or greater ceramic capacitor. provides power for the bstb and bstc driver supplies. 45 pokd open-drain power-good output for the internal source/sink linear regulator. pokd is low if fbd is more than 10% (typ) above or below the refind regulation threshold. pokd is held low during soft-start and in shutdown. pokd becomes high impedance when fbd is in regulation. 46 ond s our ce/s i nk li near reg ul ator ( reg ul ator d ) and refer ence buffer e nab l e inp ut. w hen o n d i s p ul l ed l ow , o u td i s hi g h i m p ed ance. w hen o n d i s d r i ven hi g h, the contr ol l er enab l es the sour ce/si nk l i near r eg ul ator . 47 onc switching regulator c enable input. when onc is pulled low, lxc is high impedance. when onc is driven high, the controller enables the 5a internal switching regulator. 48 fbc feedback input for the internal 5a step-down converter. fbc regulates to 0.75v. ep pgnd power ground. the source of the low-side mosfets (reg b and reg c), the drivers for all switching regulators, and the sink mosfet of the vtt ldo are all internally connected to the exposed pad. connect the exposed backside pad to system power ground planes through multiple vias. detailed description the MAX17017 standard application circuit (figure 1) provides a 5v/5a p-p main stage, a 1.8v/3a p-p vddq and 0.9a/2a vtt outputs for ddr, and a 1.05v/5a p-p chipset supply. the MAX17017 supports four power outputsone high- voltage step-down controller, two internal mosfet step-down switching regulators, and one high-current source/sink linear regulator. the step-down switching regulators use a current-mode fixed-frequency architec- ture compensated by the output capacitance. an inter- nal 50ma 5v linear regulator provides the bias supply and driver supplies, allowing the controller to power up from input supplies greater than 5.5v. fixed 5v linear regulator (ldo5) an internal linear regulator produces a preset 5v low- current output from inldo. ldo5 powers the gate dri- vers for the external mosfets, and provides the bias supply required for the smps analog controller, refer- ence, and logic blocks. ldo5 supplies at least 50ma for external and internal loads, including the mosfet gate drive, which typically varies from 5ma to 15ma per switching regulator, depending on the switching frequency. bypass ldo5 with a 4.7f or greater ceramic capacitor to guarantee stability under the full- load conditions. the MAX17017 switch-mode step-down switching reg- ulators require a 5v bias supply in addition to the main- power input supply. this 5v bias supply is generated by the controllers internal 5v linear regulator (ldo5). this boot-strappable ldo allows the controller to power up independently. the gate-driver v dd input supply is typically connected to the fixed 5v linear reg- ulator output (ldo5). therefore, the 5v ldo supply must provide ldo5 (pwm controller) and the gate- drive power during power-up.
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 17 c6 0.1 f, 6v 0402 c18 10 f, 6v 0805 r7 3.01k 1%, 0402 r8 10.0k 1%, 0402 1.05v, 4a c16 330 f 18m , 2.5v, b2 case c23 2200pf, 6v 0402 agnd agnd pwr c19 10 f, 6v 0805 pwr c20 10 f, 6v 0805 pwr c17 1 f, 6v 0402 pwr l3 1.0 h, h6.8a, 14.2m 5.8mm x 8.2mm x 3.0mm (nec/tokin: mplc0525l1r0) n l1 n h1 0.9a, 1a c5 0.1 f, 6v 0402 c7 1 f, 16v 0603 c4 0.1 f, 6v 0402 c1 4.7 f, 6v 0603 c2 1.0 f, 6v 0402 c3 0.1 f, 6v 0402 c23 0.1 f, 6v 0402 c8 4.7 f, 16v 1206 c10 22 f, 16v c-case 16tqc22m c14 150 f, 35m , 6v b2 case r5 14k 1%, 0402 r6 10.0k 1%, 0402 1.8v, 2.5a c14 330 f 18m , 2.5v, b2 case c22 1000pf, 6v 0402 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd pwr fbd agnd 2x outd ind fbc 4x lxc bstc fbb 3x lxb bstb 4x inbc byp fba csna cspa dla lxa dha bsta inldo ldo5 v dd up/dn v cc ina ona onb onc ond poka pokb pokc pokd freq sync ref vttr refind shdn agnd on off l2 1.0 h, 6.8a, 14.2m 5.8mm x 6.2mm x 3.0mm (nec/tokin: mplc0525l1ro) l1 3.3 h, 6a, 30m 6.7mm x 7.7mm x 3.0mm (nec/tokin: mplc0730l3r3) r15 4m 1% r1 10 5%, 0402 r9 100k 5%, 0402 r10 100k 5%, 0402 r11 100k 5%, 0402 r12 100k 5%, 0402 r2 0 1%, 0402 r13 15k 1%, 0402 r14 15.0k 1%, 0402 1.8v smps output 5v smps output r3 40k 1%, 0402 r4 10k 1%, 0402 c21 680pf, 6v 0402 c21 open 0402 c16 open 0402 c13 10 f, 6v 0805 c12 1 f, 16v 0402 5v, 4a 6v to 16v pwr pwr pwr pwr pwr pwr pwr c9 4.7 f, 16v 1206 pwr pwr pwr pwr on off on off on off 13 15 44 19 17 18 37 39 47 46 26 35 1 45 20 38 21 11 12 10 7, 8 9 48 3-6 2 36 31, 32, 33 34 40-43 16 25 27 29 30 28 23 24 14 22 MAX17017 pgnd figure 1. standard application circuit
MAX17017 quad-output controller for low-power architecture 18 ______________________________________________________________________________________ MAX17017 shdn refok inldo ldo5 ldo5 tsdn sw drv uvlo csb en bias en byp byp_ok v cc _ok v dd up/dn up/dn = v cc [buck], low buck mode ref_ok onldo v cc ref pgood and fault protection en en v cc osc reg a analog en v cc reg d analog v cc v cc v cc tsdn v cc ref sync *ona (shdn) ind pgnd reg d pwr outd ond fbd refind refind on_vttr vttr byp ona *buck ref enabled by shdn; boost ref enabled by ona. +ssda only used in step-up mode. ssda = high in step-down mode. onb onc ond pokx faultx onx v cc ok uvlo inbc_ok ina v cc bsta dha dla v dd cspa csna ona fba reg b analog fbb ssda+ lxa bstb v dd en en lxb inbc csc reg c analog fbc bstc v dd en lxc inbc inbc onb inbc_ok onc inbc_ok fb - + figure 2. MAX17017 block diagram
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 19 ldo5 bootstrap switchover when the bypass input (byp) exceeds the ldo5 boot- strap switchover threshold for more than 500s, an internal 1.5 (typ) p-channel mosfet shorts byp to ldo5, while simultaneously disabling the ldo5 linear regulator. this bootstraps the controller, allowing power for the internal circuitry and external ldo5 loading to be generated by the output of a 5v switching regulator. bootstrapping reduces power dissipation due to driver and quiescent losses by providing power from a switch-mode source, rather than from a much-less-effi- cient linear regulator. the current capability increases from 50ma to 100ma when the ldo5 output is switched over to byp. when byp drops below the boot- strap threshold, the controller immediately disables the bootstrap switch and reenables the 5v ldo. reference (ref) the 1.25v reference is accurate to 1% over temperature and load, making ref useful as a precision system refer- ence. bypass ref to gnd with a 0.1f or greater ceram- ic capacitor. the reference sources up to 50a and sinks 5a to support external loads. if highly accurate specifi- cations are required for the main smps output voltages, the reference should not be loaded. loading the refer- ence slightly reduces the output voltage accuracy because of the reference load-regulation error. smps detailed description fixed-frequency, current-mode pwm controller the heart of each current-mode pwm controller is a multi-input, open-loop comparator that sums multiple signals: the output-voltage error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (figure 3). the MAX17017 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. frequency selection (freq) the freq input selects the pwm mode switching fre- quency. table 1 shows the switching frequency based on the freq connection. high-frequency (freq = gnd) operation optimizes the application for the small- est component size, trading off efficiency due to higher switching losses. this might be acceptable in ultra- portable devices where the load currents are lower. low-frequency (freq = 5v) operation offers the best overall efficiency at the expense of component size and board space. fb_ ref csh_ csl_ slope compensation v l i1 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i2 i3 v bias figure 3. pwm comparator functional diagram
MAX17017 quad-output controller for low-power architecture 20 ______________________________________________________________________________________ light-load operation control the MAX17017 uses a light-load pulse-skipping operat- ing mode for all switching regulators. the switching regulators turn off the low-side mosfets when the cur- rent sense detects zero inductor current. this keeps the inductor from discharging the output capacitors and forces the switching regulator to skip pulses under light-load conditions to avoid overcharging the output. idle-mode current-sense threshold when pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current- sense threshold. under light-load conditions, the on- time duration depends solely on the idle-mode current-sense threshold. this forces the controller to source a minimum amount of power with each cycle. to avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feed- back threshold. since the zero-crossing comparator prevents the switching regulator from sinking current, the MAX17017 switching regulators must skip pulses. therefore, the controller regulates the valley of the out- put ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator senses the inductor current during the off- time. for regulator a, once v cspa - v csna drops below the 1mv zero-crossing current-sense threshold, the com- parator turns off the low-side mosfet (dla pulled low). for regulators b and c, once the current through the low- side mosfet drops below 100ma, the zero-crossing comparator turns off the low-side mosfet. the minimum idle-mode current requirement causes the threshold between pulse-skipping pfm operation and constant pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the load-current level at which pfm/pwm crossover occurs (i load(skip) ) is equivalent to half the idle-mode current threshold (see the electrical characteristics table for the idle-mode thresh- olds of each regulator). the switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load effi- ciency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load effi- ciency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using high- er inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). table 1. freq table reg a and reg c reg b switching frequency soft-start time startup blanking time switching frequency soft-start time startup blanking time pin select f swa and f swc reg a: 1200/f swa reg c: 900/f swc 1500/f swa f swb 1800/f swb 3000/f swb ldo5 250khz reg a: 4.8ms reg c: 3.6ms 6ms 500khz 3.6ms 6ms ref 375khz reg a: 3.2ms reg c: 2.4ms 4ms 750khz 2.4ms 4ms gnd 500khz reg a: 2.4ms reg c: 1.8ms 3ms 1mhz 1.8ms 3ms sync 0.5 x f sync f sync
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 21 smps por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 1.9v, resetting the undervoltage, overvolt- age, and thermal-shutdown fault latches. the por cir- cuit also ensures that the low-side drivers are pulled low until the smps controllers are activated. the v cc input undervoltage lockout (uvlo) circuitry prevents the switching regulators from operating if the 5v bias supply (v cc and v dd ) is below its 4.2v uvlo threshold. regulator a startup once the 5v bias supply rises above this input uvlo threshold and ona is pulled high, the main step-down controller (regulator a) is enabled and begins switch- ing. the internal voltage soft-start gradually increments the feedback voltage by 10mv every 12 switching cycles. therefore, outa reaches its nominal regulation voltage 1200/f swa after regulator a is enabled (see the reg a startup waveform (heavy load) graph in the typical operating characteristics ). regulator b and c startup the internal step-down controllers start switching and the output voltages ramp up using soft-start. if the bias sup- ply voltage drops below the uvlo threshold, the controller stops switching and disables the drivers (lx_ becomes high impedance) until the bias supply voltage recovers. once the 5v bias supply and inbc rise above their respective input uvlo thresholds ( shdn must be pulled high to enable the reference), and onb or onc is pulled high, the respective internal step-down con- troller (regulator b or c) becomes enabled and begins switching. the internal voltage soft-start gradually increments the feedback voltage by 10mv every 24 switching cycles for regulator b or every 12 switching cycles for regulator c. therefore, outb reaches its nominal regulation voltage 1800/f swb after regulator b is enabled, and outc reaches its nominal regulation voltage 900/f swc after regulator c is enabled (see the reg b startup waveform (heavy load) and reg c startup waveform (heavy load) graphs in the typical operating characteristics ). smps power-good outputs (pok) poka, pokb, and pokc are the open-drain outputs of window comparators that continuously monitor each output for undervoltage and overvoltage conditions. pok_ is actively held low in shutdown ( shdn = gnd), standby (ona = onb = onc = gnd), and soft-start. once the soft-start sequence terminates, pok_ becomes high impedance as long as the output remains within 8% (min) of the nominal regulation voltage set by fb_. pok_ goes low once its corresponding output drops 12% (typ) below its nominal regulation point, an output overvoltage fault occurs, or the output is shut down. for a logic-level pok_ output voltage, connect an external pullup resistor between pok_ and ldo5. a 100k pullup resistor works well in most applications. smps fault protection output overvoltage protection (ovp) if the output voltage rises above 112% (typ) of its nomi- nal regulation voltage, the controller sets the fault latch, pulls pok_ low, shuts down the respective regulator, and immediately pulls the output to ground through its low-side mosfet. turning on the low-side mosfet with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. however, this commonly undamped response causes negative output voltages due to the energy stored in the output lc at the instant the ovp occurs. if the load cannot tol- erate a negative voltage, place a power schottky diode across the output to act as a reverse-polarity clamp. if the condition that caused the overvoltage persists (such as a shorted high-side mosfet), the input source also fails (short-circuit fault). cycle v cc below 1v or toggle the respective enable input to clear the fault latch and restart the regulator. output undervoltage protection (uvp) each MAX17017 includes an output undervoltage (uvp)-protection circuit that begins to monitor the out- put once the startup blanking period has ended. if any output voltage drops below 88% (typ) of its nominal regulation voltage, the uvp protection immediately sets the fault latch, pulls the respective pok output low, forces the high-side and low-side mosfets into high- impedance states (dh = dl = low), and shuts down the respective regulator. cycle v cc below 1v or toggle the respective enable input to clear the fault latch and restart the regulator. thermal-fault protection the MAX17017 features a thermal-fault-protection cir- cuit. when the junction temperature rises above +160c, a thermal sensor activates the fault latch, pulls all pok outputs low, and shuts down all regulators. toggle shdn to clear the fault latch and restart the controllers after the junction temperature cools by 15c.
MAX17017 quad-output controller for low-power architecture 22 ______________________________________________________________________________________ vtt ldo detailed description vtt ldo power-good output (pokd) pokd is the open-drain output of a window comparator that continuously monitors the vtt ldo output for undervoltage and overvoltage conditions. pokd is actively held low when the vtt ldo is disabled (ond = gnd) and soft-start. once the startup blanking time expires, pokd becomes high impedance as long as the output remains within 6% (min) of the nominal reg- ulation voltage set by refind. pokd goes low once its corresponding output drops or rises 12% (typ) beyond its nominal regulation point or the output is shut down. for a logic-level pokd output voltage, connect an external pullup resistor between pokd and ldo5. a 100k pullup resistor works well in most applications. vtt ldo fault protection ldo output overvoltage protection (ovp) if the output voltage rises above 112% (typ) of its nomi- nal regulation voltage, the controller sets the fault latch, pulls pokd low, shuts down the source/sink linear reg- ulator, and immediately pulls the output to ground through its low-side mosfet. turning on the low-side mosfet with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. cycle v cc below 1v or toggle ond to clear the fault latch and restart the linear regulator. ldo output undervoltage protection (uvp) each MAX17017 includes an output undervoltage pro- tection (uvp) circuit that begins to monitor the output once the startup blanking period has ended. if the source/sink ldo output voltage drops below 88% (typ) of its nominal refind regulation voltage for 5ms, the uvp protection sets the fault latch, pulls the pokd out- put low, forces the output into a high-impedance state, and shuts down the linear regulator. cycle v cc below 1v or toggle ond to clear the fault latch and restart the regulator. smps design procedure (step down regulators) firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: ? input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high ac- adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. ? maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. ? switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . ? inductor operating point. this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency, higher output ripple, and lower maximum load current, and due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to oper- ate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping (light loads), the inductor value also determines the load- current value at which pfm/pwm switchover occurs. step-down inductor selection the switching frequency and inductor operating point determine the inductor value as follows: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. most inductor manufacturers provide inductors in standard values, such as 1.0h, 1.5h, 2.2h, 3.3h, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. for l vvv vf i lir out in out in sw load max = () ? ()
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 23 the selected inductance value, the actual peak-to-peak inductor ripple current ( i inductor ) is defined by: ferrite cores are often the best choice, although soft sat- urating molded core inductors are inexpensive and can work well at 500khz. the core must be large enough not to saturate at the peak inductor current (i peak ): smps output capacitor selection the output filter capacitor selection requires careful evaluation of several different design requirements stability, transient response, and output ripple volt- agethat place limits on the output capacitance and esr. based on these requirements, the typical applica- tion requires a low-esr polymer capacitor (lower cost but higher output-ripple voltage) or bulk ceramic capacitors (higher cost but low output-ripple voltage). smps loop compensation voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the loop gain. this reduces the output capacitance requirement (stability and transient) and output power dissipation requirements as well. the load-line is generated by sens- ing the inductor current through the high-side mosfet on-resistance, and is internally preset to -5mv/a (typ) for regulator b and -7mv/a (typ) for regulator c. the load- line ensures that the output voltage remains within the regulation window over the full-load conditions. the load line of the internal smps regulators also pro- vides the ac ripple voltage required for stability. to maintain stability, the output capacitive ripple must be kept smaller than the internal ac ripple voltage, and crossover must occur before the nyquist pole (2f sw )/(1+d) occurs. based on these loop requirements, a minimum output capacitance can be determined from the following: when using only ceramic capacitors on the output, the required output capacitance is: where r droop is 2r sense for regulator a, 5mv/a for regulator b, or 7mv/a for regulator c as defined in the electrical characteristics table, and f sw is the switching frequency selected by the freq setting (see table 1). when using only polymer capacitors on the output, the additional esr of the output (r esr ) must be taken into consideration. for duty cycles less than 40% using polymer capacitors: for duty cycles above 40% using polymer capacitors, the esr and c out must meet the conditions listed below: when the esr condition described above is not satis- fied, or when using a mix of ceramic and polymer capacitors on the output, an additional feedback pole- capacitor from fb to analog ground (c fb ) is necessary to cancel the output capacitor esr zero: where r fb is the parallel impedance of the fb resistive divider. smps output ripple voltage with polymer capacitors, the effective series resistance (esr) dominates and determines the output ripple volt- age. the step-down regulators output ripple voltage (v ripple ) equals the total inductor ripple current ( i inductor ) multiplied by the output capacitors esr. therefore, the maximum esr to meet the output ripple voltage requirement is: where f sw is the switching frequency. the actual capa- citance value required relates to the physical case size needed to achieve the esr requirement, as well as to the capacitor chemistry. thus, polymer capacitor selec- tion is usually limited by esr and voltage rating rather than by capacitance value. alternatively, combining ceramics (for the low esr) and polymers (for the bulk capacitance) helps balance the output capacitance vs. output ripple voltage requirements. r vf l vv v v esr in sw in out out ripple () ? ? ? ? ? ? ? ? ? c c out r r fb fb esr > ? ? ? ? ? ? rr v v c fr v v v v esr droop out fb out sw droop fb out out in < > ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? 1 2 1 c fr r xv v v v v v out sw droop esr fb out fb out out in > + () ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? 1 2 1 / c fr v v v v out sw droop fb out out in > ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? 1 2 1 ii i peak load max inductor =+ ? ? ? ? ? ? () 2 i vvv vf l inductor out in out in sw = () ?
MAX17017 quad-output controller for low-power architecture 24 ______________________________________________________________________________________ internal smps transient response the load-transient response depends on the overall output impedance over frequency, and the overall amplitude and slew rate of the load step. in applica- tions with large, fast load transients (load step > 80% of full load and slew rate > 10a/s), the output capacitors high-frequency responseesl and esrneeds to be considered. to prevent the output voltage from spiking too low under a load-transient event, the esr is limited by the following equation (ignoring the sag due to finite capacitance): where v step is the allowed voltage drop, i load(max) is the maximum load step, and r pcb is the parasitic board resistance between the load and output capacitor. the capacitance value dominates the midfrequency output impedance and dominates the load-transient response as long as the load transients slew rate is less than two switching cycles. under these conditions, the sag and soar voltages depend on the output capacitance, inductance value, and delays in the tran- sient response. low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sud- den load step, especially with low differential voltages across the inductor. the sag voltage (v sag ) that occurs after applying the load current can be estimated by the following: where d max is the maximum duty factor (see the electrical characteristics table), t is the switching peri- od (1/f osc ), and t equals v out /v in x t when in pwm mode, or l x i idle /(v in - v out ) when in pulse-skipping mode. the amount of overshoot voltage (v soar ) that occurs after load removal (due to stored inductor ener- gy) can be calculated as: when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the i rms requirements of an individual regulator can be determined by the following equation: the worst-case rms current requirement occurs when operating with v in = 2v out . at this point, the above equation simplifies to i rms = 0.5 x i load. however, the MAX17017 uses an interleaved fixed-frequency archi- tecture, which helps reduce the overall input rms cur- rent on the inbc input supply. for the MAX17017 system (ina) supply, nontantalum chemistries (ceramic, aluminum, or os-con) are pre- ferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. for the MAX17017 inbc input supply, ceramic capacitors are preferred on input due to their low parasitic inductance, which helps reduce the high-frequency ringing on the inbc supply when the internal mosfets are turned off. choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. bst capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate charging requirements of the high-side mosfets. for these low-power applica- tions, 0.1f ceramic capacitors work well. regulator a power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moder- ate-sized package (i.e., 8-pin so, dpak, or d 2 pak), i i v vvv rms load in out in out = ? ? ? ? ? ? () ? v il cv soar load max out out () () 2 2 v li cvd v itt c sag load max out in max out load max out = () () + () ? ? ? () () 2 2 r v i r esr step load max pcb ? ? ? ? ? ? ? ()
MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 25 and is reasonably priced. ensure that the MAX17017 dla gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems might occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power-mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board (pcb) layout charac- teristics. the following switching loss calculation pro- vides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the output capacitance of n h , q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ) the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) , but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, overdesign the cir- cuit to tolerate: where i limit is the peak current allowed by the current- limit circuit, including threshold tolerance and sense- resistance variation. the mosfets must have a relatively large heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage drop low enough to prevent the low-side mosfets body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3 the load current. this diode is optional and can be removed if efficiency is not critical. regulator a step-up converter configuration regulator a can be configured as a step-up converter (figure 4). when up /dn is pulled low, regulator a oper- ates as a step-up converter (for 1 li+ cell applications). it typically generates a 5v output voltage from a 3v to 5v battery input voltage. the step-up converter uses a cur- rent-mode architecture; the difference between the feed- back voltage and a 1v reference signal generates an error signal that programs the peak inductor current to regulate the output voltage. the step-up converter is internally com- pensated, reducing external component requirements. when regulator a is configured as a step-up converter, shdn should be connected to gnd. ona is the master enable switch. ona rising enables ref and the bias block. connect ldo5 and inldo together with outa and connect byp to either outa or ina. at light loads, efficiency is enhanced by an idle mode in which switching occurs only as needed to service the load. this idle-mode threshold is determined by com- paring the current-sense signal to an internal reference. in idle mode, the synchronous rectifier shuts off once the current-sense voltage (cspa - csna) drops below 1mv, preventing negative inductor current. ii i load limit inductor = ? ? ? ? ? ? ? 2 pd n sistive v v ir l out in max load ds on re () () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ? 1 2 pd n switching iq i cv h load g sw gate oss in m () ( () = + a ax in max sw vf ) () 2 ? ? ? ? ? ? pd n sistive v v ir h out in load ds on re () () = ? ? ? ? ? ? () 2
MAX17017 quad-output controller for low-power architecture 26 ______________________________________________________________________________________ c6 0.1 f, 6v 0402 c20 10 f, 6v 0805 r7 6.04k 1%, 0402 r8 15.0k 1%, 0402 1.05v, 4a c16 220 f 18m , 2.5v, b2 case c18 2200pf, 6v 0402 agnd agnd pwr c17 10 f, 6v 0805 pwr c21 10 f, 6v 0805 pwr c22 10 f, 6v 0805 pwr c19 1 f, 6v 0402 pwr l3 1.0 h, 6.8a, 14.2m 5.8mm x 8.2mm x 3.0mm (nec/tokin: mplc0525l1r0) 0.9a, 1a c5 0.1 f, 6v 0402 c7 1 f, 16v 0603 c2 1.0 f, 6v 0402 c1 4.7 f, 6v 0603 c3 10nf , 6v 0402 c4 0.1 f, 6v 0402 c8 4.7 f, 16v 1206 c9 150 f, 35m 6v b2 case c11 220 f, 35m 6v b2 c4se r5 21.0k 1%, 0402 r6 15.0k 1%, 0402 1.8v, 2.5a c14 220 f 18m , 2.5v, b2 case c15 1000pf, 6v 0402 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd pwr fbd agnd 2x outd ind fbc 4x lxc bstc fbb 3x lxb bstb 4x inbc byp fba dha bsta dla lxa csna cspa ina sync ldo5 inldo v dd v cc ona onb onc ond poka pokb pokc pokd freq ref vttr refind agnd on off l2 1.0 h, 6.8a, 14.2m 6.7mm x 7.7mm x 3.0mm (nec/tokin: mplc0730l3r3) l1 3.3 h, 6.8a, 14.2m 5.8mm x 6.2mm x 3.0mm (nec/tokin: mplc0525l1r0) r1 10 5%, 0402 r9 100k 5%, 0402 r10 100k 5%, 0402 r11 100k 5%, 0402 r12 100k 5%, 0402 r2 0 1%, 0402 r13 15k 1%, 0402 r14 15.0k 1%, 0402 1.8v smps output 5v smps output 5v smps output r3 40k 1%, 0402 r15 0.01 1%, 0612 r4 10k 1%, 0402 c11 680pf, 6v 0402 c10 0.1 f, 6v, 0402 c13 10 f, 6v 0805 c12 1 f, 16v 0402 5v, 1a 3v to 4.5v pwr pwr pwr pwr pwr pwr pwr pwr pwr n h1 pwr on off on off on off 13 14 15 19 38 44 17 37 39 47 46 26 35 1 45 20 21 11 12 10 7, 8 9 48 3-6 2 36 31, 32, 33 34 40-43 16 25 27 29 30 28 23 24 18 22 shdn up/dn n l1 MAX17017 pgnd figure 4. standard application circuit 2, regulator a configured as step-up converter
MAX17017 step-up configuration inductor selection the switching frequency and inductor operating point determine the inductor value as follows: choose an available inductor value from an appropriate inductor family. calculate the maximum dc input cur- rent at the minimum input voltage v in(min) using con- servation of energy: calculate the ripple current at that operating point and the peak current required for the inductor: the inductors saturation current rating and the MAX17017s lxa current limit should exceed i peak and the inductors dc current rating should exceed i vin(dc,max) . for good efficiency, choose an inductor with less than 0.1 series resistance. step-up configuration output capacitor selection for boost converter, during continuous operation, the output capacitor has a trapezoidal current profile. the large rms ripple current in the output capacitor must be rated to handle the current. the rms current is greatest at i load(max) and minimum input working volt- age. therefore, the output capacitor should be chosen with a rating at least i cout(rms). the rms current into the capacitor is then given by: the total output voltage ripple has two components: the capacitive ripple caused by the charging and discharg- ing of the output capacitance, and the resistive ripple due to the capacitors equivalent series resistance (esr): and: where i peak is the peak inductor current. for polymer capacitors, the output voltage ripple is typically domi- nated by resistive ripple voltage. the voltage rating and temperature characteristics of the output capacitor must also be considered. the output ripple voltage due to the frequency-dependent term can be compensated by using capacitors of very low esr to maintain low rip- ple voltage. note that all ceramic capacitors typically have large temperature coefficient and bias voltage coefficients. the actual capacitor value in circuit is typi- cally significantly less than the stated value. step-up configuration loop compensation the boost converter small-signal model contains a right half-plane (rhp) zero. the presence of an rhp zero tends to destabilize wide-bandwidth feedback loop because during a transient, the output initially changes in the wrong direction. also when an rhp zero is pre- sent, it is difficult to obtain an adequate phase margin. rhp is determined by inductance l, duty cycle d up , and load r. the rhp is: to maintain stability, crossover must occur before the rhp. to make sure the phase margin is big enough to stabilize the circuit, the converter crossover must be kept 4 ~ 10 times slower than the rhp zero. a minimum output capacitance is determined from the following: where a step-up is equal to 1.25, which is the error amplifi- er gain divided by the current-sense gain; r cs is the cur- rent-sensing resistor. additionally, an additional feedback polecapacitor from fb to analog ground (c fb )might be necessary to cancel the unwanted esr zero of the output capacitor. c a r v vdr l out step up cs ref out up > ? ? ? ? ? ? ? ? ? 4 1 - - () ? ? ? ? f dr l rhp up = () 1 2 2 - vir ripple esr peak esr () v i c vv vf ripple c out out out in out sw () ? ? ? ? ? ? - vv v ripple ripple c ripple esr =+ () ( ) ii vv v cout rms load out in in () ? - ii i peak load max inductor =+ ? ? ? ? ? ? () 2 i vv v vfl inductor in out in out sw = () - i iv v vin dc max load max out in min (, ) () () = l v v vv iflir in out out vin load max sw = ? ? ? ? ? ? ? ? 2 - () ? ? ? ? ? quad-output controller for low-power architecture ______________________________________________________________________________________ 27
MAX17017 quad-output controller for low-power architecture 28 ______________________________________________________________________________________ in general, if the esr zero occurs before the nyquist pole, then canceling the esr zero is recommended: if: then: where r fb is the parallel impedance of the fb resistive divider. step-up configuration input capacitor selection the current in the boost converter input capacitor does not contain large square-wave currents as found in the output capacitor. therefore, the input capacitor selec- tion is less critical due to the output capacitor. however, a low esr is recommended. the rms input ripple current for a boost converter is: vtt ldo design procedure ind input capacitor selection (c ind ) the value of the ind bypass capacitor is chosen to limit the amount of ripple and noise at ind, and the amount of voltage sag during a load transient. typically, ind con- nects to the output of a step-down switching regulator, which already has a large bulk output capacitor. nevertheless, a ceramic capacitor equivalent to half the vtt output capacitance should be added and placed as close as possible to ind. the necessary capacitance value must be increased with larger load current, or if the trace from ind to the power source is long and results in relatively high input impedance. vtt ldo output voltage (fbd) the vtt output stage is powered from the ind input. the vtt output voltage is set by the refind input. refind sets the vtt ldo feedback regulation voltage (v fbd = v refind ) and the vttr output voltage. the vtt ldo (fbd voltage) and vttr track the refind voltage over a 0.5v to 1.5v range. this reference input feature makes the MAX17017 ideal for memory applica- tions in which the termination supply must track the supply voltage. vtt ldo output capacitor selection (c outd ) a minimum value of 20f or greater ceramic is needed to stabilize the vtt output (outd). this value of capac- itance limits the switching regulators unity-gain band- width frequency to approximately 1.2mhz (typ) to allow adequate phase margin for stability. to keep the capacitor acting as a capacitor within the switching regulators bandwidth, it is important that ceramic capacitors with low esr and esl be used. since the gain bandwidth is also determined by the transconductance of the output mosfets, which increases with load current, the output capacitor might need to be greater than 20f if the load current exceeds 1.5a, but can be smaller than 20f if the maxi- mum load current is less than 1.5a. as a guideline, choose the minimum capacitance and maximum esr for the output capacitor using the following: and: r esr value is measured at the unity-gain-bandwidth frequency given by approximately: once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or volt- age ripple at the output. vttr output capacitor selection the vttr buffer is a scaled-down version of the vtt regulator, with much smaller output transconductance. therefore, the vttr compensation requirements also scale. for typical applications requiring load currents up to 3ma, a 0.22f or greater ceramic capacitor is recommended (r esr < 0.3 ). f c i a gbw out load = 36 15 . rm i a esr max load _ . = 5 15 cf i a out min load _ . = 20 15 i vd lf cin rms in min max sw () () . 03 c c esr r fb out fb > ? ? ? ? ? ? esr gv dav cs out ref > ? ? ? ? ? ? () 1-
vtt ldo power dissipation power loss in the MAX17017 vtt ldo is significant and can become a limiting design factor in the overall MAX17017 design: pd vtt = 2a x 0.9v = 1.8w the 1.8w total power dissipation is within the 40-pin tqfn multilayer board power-dissipation specification of 2.9w. the typical ddr termination application does not actually continuously source or sink high currents. the actual vtt current typically remains around 100ma to 200ma under steady-state conditions. vttr is down in the microampere range, though the intel specifica- tion requires 3ma for ddr1 and 1ma for ddr2. true worst-case power dissipation occurs on an output short-circuit condition with worst-case current limit. MAX17017 does not employ any foldback current limit- ing, and relies on the internal thermal shutdown for pro- tection. both the vtt and vttr output voltages are referenced to the same refind input. applications information minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the electrical characteristics table). for the best dropout performance, use the slowest switching frequency setting (freq = gnd). however, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capaci- tance must be added (see the voltage sag and soar equations in the design procedure section). the absolute point of dropout occurs when the inductor current ramps down during the off-time ( i down ) as much as it ramps up during the on-time ( i up ). this results in a minimum operating voltage defined by the following equation: where v chg and v dis are the parasitic voltage drops in the charge and discharge paths, respectively. a rea- sonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. maximum input voltage the MAX17017 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the electrical characteristics table). operation above this maximum input voltage results in pulse skipping to avoid overcharging the output. at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. this allows the controller to maintain regulation above the maximum input voltage, but forces the con- troller to effectively operate with a lower switching fre- quency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f osc is the switching frequency selected by freq. pcb layout guidelines careful pcb layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow the MAX17017 evaluation kit layout and use the following guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mil- liohm of excess trace resistance causes a measur- able efficiency penalty. ? minimize current-sensing errors by connecting cspa and csna directly across the current-sense resistor (r sense_ ). ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes (bst_, lx_, dha, and dla) away from sensitive analog areas (ref, refind, fb_, cspa, csna). vv ft in skip out osc on min () () = ? ? ? ? ? ? 1 vvvh d vv in min out chg max out dis () =++ ? ? ? ? ? ? + () ? 1 1 MAX17017 quad-output controller for low-power architecture ______________________________________________________________________________________ 29
MAX17017 quad-output controller for low-power architecture 30 ______________________________________________________________________________________ chip information process: bicmos package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 48 tqfn t4866-2 21-0141
MAX17017 quad-output controller for low-power architecture maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/08 initial release 1 9/08 updated electrical characteristics and added regulator step-up converter configuration section 4, 5, 8, 9, 23, 25C29 2 6/09 status changed from silent to public; added leakage current specification and updated note 2 in electrical characteristics ; updated figures 1, 2, and 4; updated smps loop compensation section 1C6, 8C23, 25, 26, 29, 30

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